SystemVerilog

SystemVerilog, standardized as IEEE 1800 by the Institute of Electrical and Electronics Engineers (IEEE), is a hardware description and hardware verification language commonly used to model, design, simulate, test and implement electronic systems in the semiconductor and electronic design industry. SystemVerilog is an extension of Verilog.

Software

Verilator: a SystemVerilog Compiler

Verilator is a free, open-source SystemVerilog and Verilog simulator and compiler driven by the CHIPS Alliance and the Linux Foundation.

Key Features:

  • Compiler Approach: Unlike traditional event-driven simulators, Verilator translates Verilog and SystemVerilog code into fast, cycle-accurate C++ or SystemC models (.cpp and .h files).
  • High Performance: It executes single-threaded simulations up to 100x faster—and multithreaded simulations up to 200–1000x faster—than traditional interpreted simulators.
  • Linting and Verification: Performs deep code linting, adds assertion checks, and supports code coverage analysis and waveform tracing.

Basic Workflow

  1. Verilate: Run the verilator command with your HDL source files to generate C++ or SystemC source files inside an output directory (such as obj_dir). You can also use flags like --binary to compile everything into an executable in one step.
  2. Wrapper: Write a small C++ driver or testbench (main.cpp) that defines main() and instantiates the Verilated design model as an object.
  3. Compile and Run: Compile the generated C++ files and your wrapper with a C++ compiler (like GCC or Clang) and execute the resulting binary.