Verilog

The initial Keyword

The initial keyword causes Verilog to execute its statements at time 0. It is used not only for initialization. Here is an example of an initial section:

initial $display("Hello Verilog");

The always Keyword

always blocks contain statements whose execution is triggered by some event. Alternatively, an always block starts again when it finishes. This can create an infinite loop. Some infinite loops are useful.

D Flip-Flop in Verilog's Data Flow

An edge-sensitive D flip-flop:

module edge_d_ff(q, qbar, d, clk, clear)
  output q, qbar;
  input  d, clk ,clear;
  wire s, sbar, r, rbar, cbar;
  // input latches:
  assign cbar = ~clear;
  assign sbar = ~(rbar & s),
         s    = ~(sbar & cbar & ~clk),
         r    = ~(rbar & ~s   % ~clk),
         rbar = ~(r    & cbar & d);
  // output latch:
  assign q    = ~(s&qbar),
         qbar = ~(q & r & cbar);
endmodule

fork-join Blocks

The fork-join block is similar to the begin-end block in that it is also used to group statements. In begin-end blocks, the statements are sequential, and the delays are additive. In fork-join blocks, the statements are concurrent, and the delays are independent, or absolute from the time the fork-join block starts.

Nesting begin-end and fork-join blocks

Note that fork-join and begin-end blocks are themselves single statements. You can nest fork-join and begin-end blocks. You can also nest begin-end blocks within begin-end blocks; fork-join blocks within fork-join blocks; and begin-end blocks within fork-join blocks.

Although there are four possible ways to nest these blocks, two of the combinations are generally impractical. Nesting begin-end blocks within begin-end blocks has no benefit because all the statements are sequential already. When begin-end blocks are nested, it is usually for control flow. And nesting a fork-join block in a fork-join block is impractical unless there is a delay outside the inner fork-join block.

The $display(...) System Task

$display("Hello Verilog");
$display(a); // display variable 'a'

You may also use format specifiers, much as in C printf(...). The format specifiers are %b for binary, %d for decimal, %h for hexadecimal, %o for octal, and %s for string.

$display("The value of a is %b, The value of b is %b", a, b);

...

Other System Tasks to Print Results

The $display command has several relatives: $write, $strobe, and $monitor. $write and $strobe are very similar to $display, and $monitor is a special, more powerful command.

$write is similar to $display: They both print results when encountered. The only difference between the two is that $display automatically puts in a new line at the end of the results, whereas $write does not. If you need to print many results on a line and need to use more that a single $display statement, use $write statements for the first part(s) of the line and then a $display for the rest of the line. You could decide never to use $display, and just use $write and put a new line in manually.

$strobe

If you want to print out your results only after all values are finished changing at the current time unit, use $strobe. $strobe waits until just before time is going to advance, then it prints. With $strobe you always get the new value.

$monitor

If you want to print results as they change, use the $monitor system task. Unlike $display, which prints only once, $monitor automatically prints out whenever any of the signals it is printing changes, so you only need to call it once. Only one $monitor can be active at a time. If you want to change what is being printed, just execute another $monitor system task and the new $monitor becomes the active print-on-change system task.

Because $monitor can produce a lot of output, there are two more special system tasks for stopping and restarting $monitor. To stop the $monitor from printing, use the $monitoroff command. To restart the $monitor, use the $monitoron command. Remember that there can be only one $monitor active in your simulation at a time. The last one executed is the only one in effect.

Writing to Files

By default, Verilog puts all the output that goes to your screen into a log file called verilog.log. You can view the results of your simulation by looking at the log file.

Besides sending output to the screen and log file, Verilog can write up to thirty-one additional files at the same time. File output is accomplished by declaring an integer that is used to represent the file and then opening the file. Once the file is opened, output commands similar to the ones previously described may be used to write to the file. Here's an example:

integer f;
f = $fopen("myFile");
$fdisplay(f, "Hello Verilog File");

For each of the commands covered so far ($display, $write, $monitor, and $strobe), there is an 'f' prefixed version of the command for printing data to files. All the file output commands require the first argument to be the file integer. The other command arguments are just like those for $display.

The integers used to represent the files have exactly one bit set in them. A single $fdisplay command can write to more than one file. The trick is to use the vertical line symbol ('|')to connect the file numbers, as shown below. One other trick is the numbering of the files: 1 is reserved for the screen and log file, so the first file opened will be 2 and the next, 4.

integer file1, file2;
file1 = $fopen("file1");
file2 = $fopen("file2");

$display("The number used for file 1 is %0d", file1);
$display("The number used for file 2 is %0d", file2);

$fdisplay(file1, "Hello File 1");
$fdisplay(file2, "Hello File 2");
$fdisplay(file1 | file2, "Hello both files");
$fdisplay(file1 | file2 | 1, "Hello files and screen");

$fclose(file1);
$fclose(file2);

Advanced File IO Functions

The 2001 standard greatly enhances file input and output capabilities. The 2001 standard defines $ferror, $fflush, $fgetc, $fgets, $fread, $fscanf, $fseek, $fsscanf, $ftel, $rewind, $sformat, $swrite, $swriteb, $swriteh, $swriteo and $ungetc, as new system functions. These functions work on files opened with $fopen, when $fopen is called with a mode similar to the ANSI C fopen function call. Each of these new functions works similarly to the ANSI C functions by the same name.

Setting the Default Radix

All of the commands for formatting output can be used with or without format specifiers. When you use a format specifier, the radix for each value printed out is set individually. If you do not use a format specifier, the default radix is decimal. Often it is desirable to print out values without having to use a format specifier. When debugging, it is inconvenient to have to use a format specifier just to see a value in a different radix. Thus, Verilog provides four types of each of the output functions with a different default radix. These are named by appending 'b' for binary, 'h' for hexadecimal, and 'o' for octal to $display, $fdisplay, $write, $fwrite, $strobe, $fstrobe, $monitor, and $fmonitor.

A Hello World Example

This is a simple and easy to understand example of a Verilog program. It has been lifted from the iverilog documentation:

module main;
initial
  begin
    $display("Hello, World");
    $finish;
  end
endmodule

A Behavioral-Level Example

/* Abstract behavioral system describing a telephone */
module office_phone;
  parameter min_conversation=1, max_conversation=30, false=0, true=!false;
  event ring, incoming_call, answer, make_call, busy;
  reg off_hook;
  integer seed, missed_calls;
  initial
  begin
    seed=43; // seed for call duration
    missed_calls=0;
  end
  // someone tries to call us
  always @ incoming_call
    if (! off_hook) -> ring; // if not on the phone it rings
    else begin
    -> busy; // else they get a busy signal
    $display($time," A caller got a busy signal");
    missed_calls = missed_calls + 1;
  end
  // phone is ringing . . .
  always @ring
    begin
      $write($time," Ring Ring"); / / d o we want to answer it?
      if ($random & 'b110) begin // yes we will answer it
      -> answer;
      off_hook = true;
      $display(" answered");
    end
    else // no, we do not want to answer this phone call
    begin
      missed_calls = missed calls + 1;
      $display(" not answered missed calls =%d", missed_calls);
    end
  end
    always @make_call
      if (off_hook)
      $display($time," cannot make call phone in use");
      else
      begin
        $display($time," making call");
        off_hook = true;
      end
    always wait(off_hook == true) // we are on the phone
    begin
      // wait the call duration
      #($dist_uniform(seed, min_conversation,max_conversation))
      off_hook = false;
      $display($time," off phone");
    end // might wait about 2 hours between making calls
    always #($random & 255) -> make_call;
    // someone might call in within 4 hours
    always #($random & 511) -> incoming_call;
    // Simulate two days worth of calls
  initial #(60*24*2) $finish;
endmodule

Simulation, Synthesis and Such

You choose between simulation and synthesis by choosing a target. Note that the default target selects simulation, to be performed by running a vvp file through vvp. Targets can be set with the switch:

-t<target>

Target switches are:

null

The null target causes no code to be generated. It is useful for checking the syntax of the Verilog source.

vvp

This is the default. The vvp target generates code for the vvp runtime. The output is a complete program that simulates the design but must be run by the vvp command.

fpga

This is a synthesis target that supports a variety of fpga devices, mostly by EDIF format output. The Icarus Verilog fpga code generator can generate complete designs or EDIF macros that can in turn be imported into larger designs by other tools. The fpga target implies the synthesis -S flag.

vhdl

This target produces a VHDL translation of the Verilog netlist. The output is a single file containing VHDL entities corresponding to the modules in the Verilog source code. Note that only a subset of the Verilog language is supported. See the wiki for more information.

Minimum, Typical or Maximum Values

-Tmin|typ|max

Use this switch to select min, typ or max times from min:typ:max expressions. Normally, the compiler will simply use the typ value from these expressions (printing a warning for the first ten it finds) but this switch will tell the compiler explicitly which value to use. This will suppress the warning that the compiler is making a choice.

Module Libraries in Verilog

The Icarus Verilog compiler supports module libraries as directories that contain Verilog source files. During elaboration, the compiler notices the instantiation of undefined module types. If the user specifies library search directories, the compiler will search the directory for files with the name of the missing module type. If it finds such a file, it loads it as a Verilog source file, then tries again to elaborate the module.

Library module files should contain only a single module, but this is not a requirement. Library modules may reference other modules in the library or in the main design.

Language Version

This is called generation and is set through switches: -g1995, -g2001, -g2001-noconfig or -g2005.